Friday, January 15, 2010

Network Processors - C1

Network Processors seems to have lot of demand and supply these days. After working on 3 processors (Texas DSP TMS320C6416, Atmel ARM AT 91 and Intel NP IXP2350) in my 6 years+ professional experience, it is interesting to understand how network processors differ from the other processors.

The best way to understanding NP is in terms of a router used for processing voics/SMS packets over a digital telecom network in order of nano/micro seconds. The real trick in programming and using the network processor the most efficient way lies in making full benefit of the money paid to the selling entity by tapping its most specific features.

Lets also try to understand how network processors differ form other specialized processors e.g. viterbi coprocessors.Network processors in general work on the logic of efficient parallel processing which inevitably leads to less code space for each sub-module but the amount of data that can be processed is comparatively higher. Again try to visualize the amount of traffic crossing a router of a VOIP based network every second.

Viterbi Coprocessor (VCP) decodes convolutional codes during channel de-coding of voce/data call.VCP also decodes a series of frames in a most efficient manner. Here again VCP related effort is to maximize its processing power, and minimize the wait period for input/output operations.

So this helps in developing an understanding that VCP is specialized for 1 particular operation whereas each sub-module of NP is specialized for a partiular sub-operation. To put in other words, the key feature of a network processor is its parallel processing capacity dealing with huge number of network packets at a very fast pace.

Local memory caching is another concept widely used in NP to reduce the access time of information more frequently required by that particular thread of micro engine running in network processor. Figure below captures main blocks of IXP2400 and IXP1200 processors:

NP vocabulary mainly highlights following terms:

1. MSF: media switch fabric
2. QDR SRAM controller
3. ME: Micro Engine
4. PCI: Peripheral Component Interconnect
5.CAM: Content Addressable Memory
6. XFER: Transfer Register
7. GPR: General Purpose Register

Links for reference:


1. What disadvantages do high level languages impose if used on Network processors other than their translation time?

2. What will happen if input packet speed is more than than the data rate supported by NP; also think of scenario where packet speed is less.

3. Buffer management and data compression/decompression pose what kind of challenges to Network processors.

4. Out of TCP and UDP protocol stack, which is more apt to be supported on Motorola C5 NP?

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