References:
1. http://en.wikipedia.org/wiki/Integrating_ADC
2.courses.engr.illinois.edu/ece581/int.ppt
3. http://www.maxim-ic.com/app-notes/index.mvp/id/1041
4. http://www.allaboutcircuits.com/vol_4/chpt_13/8.html
1. Longer integration times allow for higher resolutions.
2. Their use is typically limited to digital voltmeters and other instruments requiring highly accurate measurements.
3. One of the slowest ADCs.
4. Block diagram of dual-slope ADC:
5. Integrating analog-to-digital converters (ADCs) provide high resolution analog-to-digital conversions, with good noise rejection.
7. Single-Slope ADC Architecture
The simplest form of an integrating ADC uses a single-slope architecture . Here, an unknown input voltage is integrated and the value compared against a known reference value. The time it takes for the integrator to trip the comparator is proportional to the unknown voltage (TINT/VIN). In this case, the known reference voltage must be stable and accurate to guarantee the accuracy of the measurement.
8.
Figure 2. Dual-slope integration.
The key advantage of this architecture over the single-slope is that the final conversion result is insensitive to errors in the component values. That is, any error introduced by a component value during the integrate cycle will be cancelled out during the de-integrate phase. In equation form:
Vin × TINT = VREF × TDEINT
or
TDEINT = TINT × (VIN / VREF)
From this equation, we see that the de-integrate time is proportional to the ratio of VIN / VREF. A complete block diagram of a dual-slope converter is shown in Figure 3.
1. http://en.wikipedia.org/wiki/Integrating_ADC
2.courses.engr.illinois.edu/ece581/int.ppt
3. http://www.maxim-ic.com/app-notes/index.mvp/id/1041
4. http://www.allaboutcircuits.com/vol_4/chpt_13/8.html
1. Longer integration times allow for higher resolutions.
2. Their use is typically limited to digital voltmeters and other instruments requiring highly accurate measurements.
3. One of the slowest ADCs.
4. Block diagram of dual-slope ADC:
6. It is possible to avoid using a DAC inside an ADC circuit if we substitute an analog ramping circuit and a digital counter with precise timing. in integrating single slope ADC, instead of using a DAC with a ramped output, we use an op-amp circuit called an integrator to generate a sawtooth waveform which is then compared against the analog input by a comparator.
The time it takes for the sawtooth waveform to exceed the input signal voltage level is measured by means of a digital counter clocked with a precise-frequency square wave (usually from a crystal oscillator).
7. Single-Slope ADC Architecture
The simplest form of an integrating ADC uses a single-slope architecture . Here, an unknown input voltage is integrated and the value compared against a known reference value. The time it takes for the integrator to trip the comparator is proportional to the unknown voltage (TINT/VIN). In this case, the known reference voltage must be stable and accurate to guarantee the accuracy of the measurement.
One drawback to this approach is that the accuracy is also dependent on the tolerances of the integrator's R and C values. Thus in a production environment, slight differences in each component's value change the conversion result and make measurement repeatability quite difficult to attain. To overcome this sensitivity to the component values, the dual-slope integrating architecture is used.
8.
Dual-Slope ADC Architecture
A dual-slope ADC (DS-ADC) integrates an unknown input voltage (VIN) for a fixed amount of time (TINT), then "de-integrates" (TDEINT) using a known reference voltage (VREF) for a variable amount of time (see Figure 2).Figure 2. Dual-slope integration.
The key advantage of this architecture over the single-slope is that the final conversion result is insensitive to errors in the component values. That is, any error introduced by a component value during the integrate cycle will be cancelled out during the de-integrate phase. In equation form:
Vin × TINT = VREF × TDEINT
or
TDEINT = TINT × (VIN / VREF)
From this equation, we see that the de-integrate time is proportional to the ratio of VIN / VREF. A complete block diagram of a dual-slope converter is shown in Figure 3.
9. In the dual-slope converter, an integrator circuit is driven positive and negative in alternating cycles to ramp down and then up, rather than being reset to 0 volts at the end of every cycle. In one direction of ramping, the integrator is driven by the positive analog input signal (producing a negative, variable rate of output voltage change, or output slope) for a fixed amount of time, as measured by a counter with a precision frequency clock.
Then, in the other direction, with a fixed reference voltage (producing a fixed rate of output voltage change) with time measured by the same counter. The counter stops counting when the integrator's output reaches the same voltage as it was when it started the fixed-time portion of the cycle. The amount of time it takes for the integrator's capacitor to discharge back to its original output voltage, as measured by the magnitude accrued by the counter, becomes the digital output of the ADC circuit.
Question IES 2011:
With a block diagram, explain the function of a dual slope DVM.
A dual slope integrating type of A/D converter has an integrating capacitor of 0.1 uF and a resistance of 100 k ohm. the reference voltage is 2 V and the output of the integrator is not to exceed 10 V. What is the maximum time required for the output voltage to be integrated?
Answer:
check this link:
DVM is essentially an Analog to digital converter (A/D) with a digital display.
It uses dual slope integrating type A/D converter as explained above.
Maximum time taken by integrator = R * C = .01 sec = 10 ms
relative value corresponding to 10 V = 5 * 10 ms = 50 ms.
Anybody having a different viewpoint for this problem, kindly share the same.
Anybody having a different viewpoint for this problem, kindly share the same.
